• DocumentCode
    3664686
  • Title

    Performance trade-off in decision diagram based synthesis of reversible logic circuits

  • Author

    H V Jayashree;Anmol Prakash Surhonne;V K Agrawal

  • Author_Institution
    Dept. of Electronics and Communication, PES Institute of Technology, Bangalore
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    209
  • Lastpage
    212
  • Abstract
    Reversible computing is an emerging and promising technique due to its wide applications in quantum, optical and DNA computing and many more. Reversible circuit synthesis is a main focus for researchers as conventional synthesis techniques are not suitable for reversible circuits. Our work focuses on BDD based synthesis as it has capabilities of realizing circuit for large boolean functions unlike other reversible synthesis methods. Existing BDD based synthesis techniques rely on positive [1] and negative [2] controlled Toffoli gates. In this paper work we explore BDD based synthesis technique along with evolutionary computation method. We employed Fredkin and elementary CNOT gate library. Experimental results demonstrate that this approach reduces the gate count and quantum cost at the cost of increase in the number of lines.
  • Keywords
    "Logic gates","Boolean functions","Data structures","Libraries","Conferences","Electron devices","Solid state circuits"
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
  • Print_ISBN
    978-1-4799-8362-9
  • Type

    conf

  • DOI
    10.1109/EDSSC.2015.7285087
  • Filename
    7285087