Monolithic integration of high capacitance (power/ground) and low

For both power/ground and data carrying TSVs, TSV resistance is preferred to be as low as possible. Power/ground TSVs should exhibit larger TSV capacitance so that TSV can act as a decoupling capacitor while data TSVs should exhibit low TSV capacitance enabling larger data rates. Monolithic integration scheme employing the annular isolation ring to isolate the data and power/ground TSVs is proposed to satisfy these conflicting TSV capacitance requirements. SDevice simulations as well as PD and FD M-O-S-O-S capacitance based models are used to demonstrate that the proposed architecture achieves low TSV capacitance for data TSVs and high oxide capacitance for power/ground TSVs monolithically. Manufacturing feasibility and process integration to realize the proposed structure augmenting the TSV manufacturing flow is also discussed.