DocumentCode :
3664729
Title :
Device level 3-dimensional ICs: Membrane projection lithography for advanced manufacturing
Author :
D. Bruce Burckel;Paul J. Resnick;Bruce L. Draper;Patrick S. Finnegan;Paul Davids
Author_Institution :
Sandia National Laboratories, P.O. Box 5800, Albuquerque, New Mexico, USA 87185
fYear :
2015
fDate :
6/1/2015 12:00:00 AM
Firstpage :
379
Lastpage :
382
Abstract :
Membrane projection lithography (MPL) is proposed as a method for creation of 3-dimensional integrated circuits at the device level as opposed to stacking 2-D die. In MPL, standard semiconductor fabrication processes and equipment are used in a novel sequence of processing steps to create 3 dimensional micrometer-scale structures. Generalization of MPL from strictly deposition to ion implantation and dry etching, combined with blanket processes such as CVD deposition and oxidation, provide all the necessary ingredients for fabrication of integrated circuit devices in all three coordinate axes in high topography silicon.
Keywords :
"Fabrication","Silicon","Lithography","Integrated circuits","Etching","Implants","Standards"
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
Print_ISBN :
978-1-4799-8362-9
Type :
conf
DOI :
10.1109/EDSSC.2015.7285130
Filename :
7285130
Link To Document :
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