A DCO compiler for all-digital PLL design

In this paper, we present a digitally controlled oscillator (DCO) compiler for reducing design turn around time for an all-digital phase-locked loop (ADPLL). According to user input specifications, the DCO compiler can generate the DCO netlist implemented with standard cells and the command scripts for automatically placement and routing. The proposed DCO compiler uses liberty timing files (.lib) to compute the cell delay, and the proposed DCO regular placement approach makes it easy to predict the wire capacitance of the DCO. As a result, the frequency range of the DCO can be estimated accurately. Furthermore, a frequency estimation algorithm is presented to reduce the lock-in time of the ADPLL. The proposed ADPLL and the DCO compiler are simulated in 90nm CMOS process. In post-layout simulation, the maximum frequency range estimation error of the proposed DCO compiler is 6.65% with process, voltage, and temperature variations. In addition, the frequency error of the proposed fast settling ADPLL can be smaller than 2% within four clock cycles with different input multiplication ratio.