Berger check and fault tolerant reversible arithmetic component design

In order to continue the revolution in the computer hardware performance, we need to reduce the energy dissipated in each logic operation. Energy dissipation can be reduced by preventing information loss. This is achieved by designing the circuits using reversible logic gates. It has wider applications in the fields of quantum computing, nanotechnology, and many more. Fault Tolerant logic has become a very important technique in the present day electronics, in order to minimize the errors in the circuit. Fault Tolerant gates with error detection capability, turns down the need for any external hardware to test the circuit. In this paper, we have proposed a reversible Fault Tolerant Adder/Subtractor and also a Berger check prediction circuit to check all unidirectional and multiple errors for all reversible Adders/Subtractors. This is the first attempt in the literature to implement a Berger check logic using reversible gates. The performance parameters of both reversible Berger check logic and the Fault Tolerant reversible logic has been compared and analyzed. Fault Tolerant logic, though it doesn´t require any external hardware, the quantum cost is found to be 25% more than Berger check logic and garbage outputs required is 75% more, similarly ancilla inputs is 25%, gate count is 45% and delay of circuit is 30% more than the proposed Berger check circuit. Hence, the Berger check circuit is found to more efficient in terms of quantum cost, delay and gate count.