Validation of a MMC model in a real-time simulation platform for industrial HIL tests

The VSC based HVDC link between France and Spain (INELFE project: France-Spain ELectrical INterconnection) will be the most powerful HVDC-VSC link by 2015. This 2000 MW interconnection is comMMC modelposed of 2 independent VSC type links. For system studies and maintenance purposes, replicas of the control systems are acquired by the French (RTE) and the Spanish (REE) Transmission System Operators. This paper describes the setup to perform Hardware In the Loop (HIL) simulations with the INELFE control system replicas. Surge arresters are used in MMC converters to limit overvoltages during DC perturbances and converter internal faults. The nonlinear characteristics of this equipment shall be modeled when DC faults or internal converter faults are analyzed in offline and real-time simulations. The paper presents how this equipment are taken into account in order to be able to test the control system with AC and DC faults. A complete setup has been developed in order to validate the modeling approach. Hardware-In-the-Loop (HIL) simulations have been performed which includes the real-time simulator connected to an external generic control system having the same interface than the replica.