Title :
TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment
Author :
C. Tavernier;F. G. Pereira;O. Nier;D. Rideau;F. Monsieur;G. Torrente;M. Haond;H. Jaouen;O. Noblanc;Y.M. Niquet;M-A. Jaud;F. Triozon;M. Casse;J. Lacord;J.C Barbe
Author_Institution :
STMicroelectronics, Technology and Platform Development, 850 Cours Jean Monnet, F-38926 Crolles, France
Abstract :
This paper reviews the main challenges for the TCAD of 14nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology performance assessment. Thanks to a multi-scale approach combining extensive electrical characterization and advanced solvers simulations, ensuring deep physical insight, we provide TCAD simulation framework for device layout optimization, strain engineering and device reliability assessment.
Keywords :
"Logic gates","Performance evaluation","Semiconductor device modeling","MOS devices","Silicon germanium","Resistance","Computational modeling"
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on
Print_ISBN :
978-1-4673-7858-1
DOI :
10.1109/SISPAD.2015.7292244
