DocumentCode
3667926
Title
Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond
Author
A. Idrissi-El Oudrhiri;S. Martinie;J-C. Barbé;O. Rozeau;C. Le Royer;M-A. Jaud;J. Lacord;N. Bernier;L. Grenouillet;P. Rivallin;J. Pelloux-Prayer;M. Cassé;M. Mouis
Author_Institution
CEA-LETI, Campus MINATEC, 17 rue des Martyrs, 38054 Grenoble, Cedex 9, France
fYear
2015
Firstpage
206
Lastpage
209
Abstract
Stress engineering is a powerful tool to enhance nanoscale device performances. In this study we developed a methodology of 14nm strained pMOS FDSOI device mechanical simulation in order to carefully evaluate different stress effects on device performances. Mechanical simulation results are presented for different process solutions, such as Gate-First (GF) and Gate-Last (GL) processes but also for variation of germanium contents in source/drain and channel regions.
Keywords
"Stress","Logic gates","Epitaxial growth","MOSFET","Tin","Strain","Silicon germanium"
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on
ISSN
1946-1569
Print_ISBN
978-1-4673-7858-1
Type
conf
DOI
10.1109/SISPAD.2015.7292295
Filename
7292295
Link To Document