DocumentCode :
3668956
Title :
An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimization
Author :
Henry Block;Tsutomu Maruyama
Author_Institution :
Systems and Information Engineering, University of Tsukuba, 1-1-1 Ten-ou-dai 305-8573 JAPAN
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, we present an alternative and improved FPGA hardware implementation for a phylogenetic tree reconstruction with maximum parsimony algorithm. As in our previous work, the approach is based on a particular stochastic local search algorithm that uses the Indirect Calculation of Tree Lengths method. However, now we use an alternative second-pass optimization method, for the first time, and modify the rearrangement evaluation process. As a result, we reduce the execution time by half for these two steps in the algorithm. We compare execution times against our previous hardware approach for six real-world biological datasets, obtaining an acceleration rate of around 1.2 times faster. We also show a comparison against the phylogenetic software TNT.
Keywords :
"Phylogeny","Hardware","Topology","Field programmable gate arrays","Acceleration","Optimization methods"
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2015 25th International Conference on
Type :
conf
DOI :
10.1109/FPL.2015.7293973
Filename :
7293973
Link To Document :
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