Pipelined NoC router architecture design with buffer configuration exploration on FPGA

Emerging System-on-Chip (SoC) applications on FPGAs have boosted the FPGA-based Network-on-Chip (NoC) implementations. Router microarchitecture plays a central role in the performance of an NoC. This paper investigates the router architecture in great detail and designs high throughput architecture based on the fine-grained configurability and customizability provided by FPGAs. Specifically, we 1) divide the logic operations of the router into two pipelining stages and implement a modified backpressure flow control mechanism to support high frequency and pipelined routing operation; 2) explore different buffering schemes to find an architecture which can sustain low queuing delays. The experimental results show that the pipelined architecture achieves operation clock frequency over 400 MHz, which is 3 times higher than that of an open source FPGA-based NoC, CONNECT, leading to about 5 times improvement in the network saturation throughput.