FPGA-based all-digital Software Defined Radio receiver

In this Ph.D. work it is intended to explore innovative agile and wideband FPGA-based Software Defined Radio (SDR) receiver architectures for future 5G wireless communications. This short paper presents some preliminary work in this area, including interesting results of an innovative SDR receiver. This new architecture implements the analog-to-digital conversion directly at RF stage based on Pulse Width Modulation (PWM). The system is implemented using the high speed differential input buffers of a medium range FPGA as a comparator. Simulation and measured results will be presented and evaluated in terms of Signal-to-Noise Ratio (SNR) and Error Vector Magnitude (EVM). Briefly, this architecture allows an input bandwidth of almost 3GHz maintaining an EVM below 2% for a 2MHz wide signal.