Hybrid FPGA debug approach

In the modern verification environment an FPGA-based prototyping has become an important part of the whole verification flow. The ability to simulate real time application in more realistic speeds allows much higher coverage than traditional HDL logic simulators. The main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently there are two traditional solutions for this problem. The first solution is using embedded trace-buffers to record a subset of internal signals and the second solution captures a snapshot of the current FPGA state. Both of these techniques have certain benefits and shortcomings. In this paper, we present an idea of merging these two techniques into a new hybrid approach. Using this idea we created a hybrid circuit and during our experiments showed that it preserves all good sides from both traditional approaches.