• DocumentCode
    3670356
  • Title

    Chip-level and package-level thermal constraints in power semiconductor switch modules

  • Author

    Krishna Shenai

  • Author_Institution
    LoPel Corporation, Naperville, Illinois (USA)
  • fYear
    2015
  • fDate
    5/1/2015 12:00:00 AM
  • Firstpage
    79
  • Lastpage
    82
  • Abstract
    A simple model for heat generation and heat spreading, and temperature rise of the active region of a power semiconductor switch is presented by properly accounting for semiconductor and package thermal and heat capacity parameters. The model is used to estimate the effect of finite substrate thickness in silicon and wide bandgap (WBG) power switching devices on junction temperature rise. Whereas 4H-SiC power devices show superior thermal performance compared to either GaN or silicon power devices, calculations suggest the need to thin down the current state-of-the-art 4H-SiC substrates by at least a factor of two, and the need to increase thermal conductivity of GaN substrates. The model is also used to estimate the power-handling capability of power switch modules, and the experimental data is shown to be in good agreement with the theoretical model for 1700V/25A 4H-SiC JBS power diodes.
  • Keywords
    "Substrates","Heating","Silicon","Temperature measurement","Semiconductor device modeling","Semiconductor diodes","Electric fields"
  • Publisher
    ieee
  • Conference_Titel
    Integrated Power Packaging (IWIPP), 2015 IEEE International Workshop on
  • Type

    conf

  • DOI
    10.1109/IWIPP.2015.7295983
  • Filename
    7295983