On the reliability and efficiency of novel programming architectures for next-generation flash memories

NAND Flash memories are currently the most popular non-volatile memory elements. Multi-level memory cells and the technologic possibility of producing very small memory cells lead their storage capacity to increase enormously, and yet the aim of the next-generation Flash memory producers is to build smaller and denser memory cells. On the other hand, these improvements make the performance of these devices considerably unreliable since major error sources are significantly amplified as the Flash memories get smaller and denser. In this paper, we study the error performance and also information theoretic channel capacity of conventional and proposed programming methods for Flash memories. Our computer simulation results indicate that the proposed methods can not only improve the error performance, but also increase the transmission efficiency by delivering a higher channel capacity under severe-interference channel, which is the scenario for the next-generation Flash memories.