Spacer lithography for 3D MOS devices using amorphous silicon deposited by ECR-CVD

In this work, hydrogenated amorphous silicon (a-Si:H) films were deposited by electron cyclotron resonance (ECR) - chemical vapor deposition (CVD) and used as spacer to implement the spacer lithography (SL) technique. This technique was employed to define silicon nanowires (SiNWs), which are three-dimensional (3D) structures on Si surface. With these SiNWs, 3D MOS (metal-oxide-semiconductor) capacitors were fabricated. Surface analyses were carried out by atomic force microscopy (AFM) and scanning electron microscopy (SEM) in order to verify the quality and integrity of SiNWs. From these measurements, it can be observed continuous and lengthy SINWs with heights of 17.7 nm and widths of 15.6 nm. Furthermore, the fabricated 3D MOS capacitors, with Al (500 nm)/ SiO₂ (10 nm)/ SiNWs structures, were used to obtain capacitance-voltage (CxV) measurements. From CxV curves, it can be observed that the capacitors exhibited a perfectly defined, the accumulation, depletion and inversion regions of carriers in the Si substrate with SiNWs. Furthermore, also the effective charge density of about 10¹¹ cm^-2 and flat-band voltage of -1.1 V were extracted. From these results, it can be concluded that the proposed method of spacer lithography can be used to get 3D MOS devices, such as FinFETs and JunctionLess, which are based on SiNWs.