A 65 nm standard cell library for ultra low-power applications

This paper describes the development of a 65nm standard cell library designed for building highly energy-efficient digital circuits. In total 43 logic cells and 19 special cells for clock-tree synthesis and place and route purposes are implemented using a commercial 65 nm bulk technology. As a result full-chip implementation of low-power systems operating at ultra-low voltage is feasible. The benefits of this subthreshold cell design are demonstrated by synthesis and analysis of a sample circuit for supply voltages from 250 mV to 1.2 V. Power analysis at gate-level shows an improvement in energy consumption by a factor of 9.25 with a total energy consumption of 11.7pJ per clock cycle in the subthreshold domain.