A novel forward body biasing technique for subthreshold ring oscillators

In this paper, a new forward body biasing scheme is proposed for CMOS inverters used in subthreshold ring oscillators (ROs). In the proposed scheme by using auxiliary transistors higher forward body biasing voltage magnitudes are achieved compared with the conventional forward body biasing (FBB) schemes. In the literature swapped body biasing (SBB) and dynamic threshold MOSFET (DTMOS) are conventionaly used to obtain forward body biasing in the transistor. Three-stage ROs are designed for the target frequency of 13.56 MHz by using the proposed and the conventional FBB techniques in CMOS inverters. The architectures are implemented in a standard 0.18 μm CMOS technology. Post layout simulations (PLS) are performed using the Cadence Spectre simulator. The power dissipation is selected as a figure of merit (FOM) to evaluate the performances of ROs. PLS results show that with subthreshold supply voltages, the RO using the proposed forward biasing scheme consumes 451nW of power. This power dissipation is 30% less compared with SBB based RO and 48% less compared with DTMOS based RO.