Integration of QMC based yield-aware pareto front techniques on MOEA/D for robust analog synthesis

This paper focuses on the implementation of different techniques for the integration of yield in the synthesis loop of analog ICs. Several algorithms have been developed for multi-objective optimization. Among these optimizers, MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is known as a powerful synthesizer. By using MOEA/D, some quality checks on practical designs have been realized in order to show the algorithm is well-suited for robust multi-objective optimization of analog circuits. Another issue that is considered is the inclusion of yield for obtaining robust PFs for analog sizing problems. Several techniques are discussed and three different yield-aware PF techniques have been implemented on MOEA/D. The implemented yield-aware PF techniques are compared by using a fully-differential folded-cascode amplifier. The results suggest that all three of these techniques look promising for high dimensional robust optimization of analog circuits.