DocumentCode :
3674324
Title :
A causal reasoning-based approach for analog circuit verification
Author :
Fanshu Jiao;Alex Doboli
Author_Institution :
Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
This paper proposes a novel analog circuit verification approach using causal reasoning. To verify analog circuits, the flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justification [1]. Then, topological structures corresponding to the starting ideas and design step sequences are verified individually by replacing the related devices with ideal amplifier model. Circuit performance is evaluated through Spectre simulation. Comparing simulation results reveals incorrect functional issues and/or performance drawbacks (negative causes) of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.
Keywords :
"Analog circuits","Performance evaluation","Cognition","Integrated circuit modeling","Mirrors","Simulation","Noise"
Publisher :
ieee
Conference_Titel :
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on
Type :
conf
DOI :
10.1109/SMACD.2015.7301711
Filename :
7301711
Link To Document :
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