Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip Multiprocessor

Chip Multiprocessors (CMPs) composed of more than 1000 cores are expected to be manufactured before the end of next decade. Conventional wired interconnects are already incapable to provide the necessary high throughput and low latency to multiprocessors of this scale. Thus, on-chip Radio Frequency (RF) and optical interconnects are proposed recently to surpass communication limits. However, these interconnect structures fail to provide essential requirements of bandwidth reconfigurability and broadcast support with a low complex design. In this work, we evaluate an OFDMA based on-chip RF interconnect with a flexible bandwidth infrastructure, that exploits the bimodal packet sizes of on-chip traffic, while requiring no signaling overhead or complex circuitry. It is shown that it can provide up to x3.5 less average latency compared to a static system with no flexibility.