DocumentCode
3674752
Title
A Low Power 64-point Bit-Serial FFT Engine for Implantable Biomedical Applications
Author
Lang Yang;Thomas W. Chen
fYear
2015
Firstpage
383
Lastpage
389
Abstract
Implantable biomedical devices are typically battery operated. Therefore they normally have stringent constrains on power consumption and size. This paper presents a low power 64-point, 16-bit fixed-point Fast Fourier Transform(FFT) processor design. Bit-serial logic was used in the design to achieve low power while maintain sufficient performance for biomedical applications. The proposed FFT design was implemented in a commercial 0.18um CMOS process with a power supplier of 1.8V and running at 50MHz clock rate. The power consumption of 14mW with 0.55Mpoints/s signal throughput is achieved.
Keywords
"Complexity theory","Adders","Power demand","Clocks","Time-domain analysis","Performance evaluation","Transistors"
Publisher
ieee
Conference_Titel
Digital System Design (DSD), 2015 Euromicro Conference on
Type
conf
DOI
10.1109/DSD.2015.30
Filename
7302300
Link To Document