Time-Triggered Extension Layer for On-Chip Network Interfaces in Mixed-Criticality Systems

The increasing trend towards mixed-criticality in different domains demands a platform in which the physical integration of subsystems with different criticalities is accommodated. A fundamental prerequisite for such a platform is to establish temporal and spatial segregation between different subsystems in order to eliminate the interference on safety-critical functions, caused by non-safety-critical ones. Furthermore, as mixed-criticality systems often comprise heterogeneous subsystems, the platform shall support different timing models (e.g., periodic and sporadic activities). This paper introduces an extension layer for the Network Interface (NI) of a network-on-a-chip in order to establish the temporal and spatial partitioning over the entire chip. We describe how chip-wide temporally aligned activities of different NIs in combination with resource allocations assure the absence of interference for time-triggered messages and bounded latencies for rate-constrained messages. The chip-wide configuration of the NIs establishes guarding windows for time-triggered messages and traffic shaping of rate-constrained messages.