Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic

This paper addresses two common problems of soft error handling schemes for sequential logic. The first issue is a race condition between the correction of soft errors and their propagation to following stages. The second issue concerns erroneous write accesses to external memory. Both problems are thoroughly examined. The key idea in order to resolve the problems is to distinguish between different types of transient faults (soft errors, timing violations) and explicitly utilize their individual characteristics. Based on that principle a low-cost shadow cell is proposed. Transient faults are detected by shadowing the interfaces of a flip-flop. Timing violations and early soft errors are corrected by architectural replay. Late soft errors are instantly corrected within the shadow cell. The introduced area overhead is 57% and the power overhead 32% compared to a standard cell D-flip-flop.