Introducing embedded patterned layers for improved broadband performance of high density transmission line routing

The gate lengths in metal oxide semiconductor field effect transistors (MOSFETs) have shrunk from 10um in 1970s to 28nm in 2011, which is the result of intensive research in the field of active device physics and fabrication. Smaller transistor features have increased the transistor density in high frequency integrated circuits (ICs) allowing the semiconductor industry to follow Moore´s Law. High frequency circuit designs, such as those used in T/R modules, take advantage of increased circuit transistor density to boost the number of processes and functionalities. So, the number of signal input/output (I/O) must also increase in tandem to support these functionalities and to meet the demands of higher transmission rates. However, real estate is limited on chip, package and at the system level, which requires creative solutions to route interconnects in close proximity to one another. This makes electromagnetic effects due to interconnect delay, crosstalk noise etc. performance limiting factors that must be addressed.