Design and Correctness

This session presents a domain-specific language for high-level synthesis of hardware for FPGA platforms and describes its memory management for pipelined target architectures. It also presents a methodology to construct test sequences starting from PSL assertions and design under test written in VHDL using VSYML and SyntHorus tools. Finally it presents a top-down design flow to refine an architecture level description of a system into an RTL implementation, while refining operation properties concurrently.