Optimal switching of SiC lateral MOSFETs

The switching loss of the 1700 V SiC Planar-Gate MOSFET is significant at switching frequencies above 2 kHz. If a simple resistive gate driver is adjusted for the worst case operating point (temperature, commutated voltage and current) with a given application dV/dt requirement, other operating points usually have lower dV/dt resulting in non-optimal losses. The paper shows results of an optimized gate-drive solution, adapting a current source control in order to reduce the losses while fulfilling the application dV/dt requirements.