Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power

In this paper, we propose a new sub-threshold 9T-Static Random Access Memory (SRAM) cell in 14 nm Fin FET technology by which the access time of the memory cell is improved by at least 30 percent compared to the standard 8T-SRAM cell. Furthermore, the leakage current of the proposed SRAM cell is reduced by an assisting circuit. Simulation results show that the leakage of the proposed cell is reduced by 20% after using the technique. Furthermore, the read access time of the proposed cell is reduced by 30% compared to the 8T-SRAM cell while write margin and read noise margin of the proposed cell is not degraded. The maximum operating frequency for the proposed SRAM cell is 2.7 MHz at VDD=200 mV.