Modulo 2n ± 1 Fused Add-Multiply Units

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. Targeting to increase performance, in this work, we focus on optimizing the design of the modulo 2n ± 1 Add-Multiply (AM) operation. The proposed modulo 2n ± 1 fused AM units incorporate an initial row of Half Adders which carry out the requested addition of two specified operands resulting to an intermediate Delayed Carry representation of their sum. The Delayed Carry represented vectors are then multiplied by the specified multiplicand and the partial products are driven to OR logic gates in pairs. Using the appropriate Carry-Save (CS) Adder trees, the resulting n-bit operands are reduced to a pair of CS vectors, which are finally added by a modulo 2n -- 1 or a modulo 2n + 1 adder. Compared to the conventional designs of first instantiating a modulo 2n ± 1 adder and then, driving its output to a modulo 2n ± 1 multiplier, the proposed fused AM designs yield considerable reductions in terms of critical delay, area complexity and power consumption.