High throughput floating point exponential function implemented in FPGA

Three new high throughput FPGA floating point implementations of the power series based exponential function algorithm are proposed. Evaluations of three exponential function algorithms suitable for hardware implementation are also presented. The hardware implementations use 32-bit floating point single precision. The proposed hardware implementation calculates the new exponential function result in every 11 clock cycles. The proposed hardware implementations are designed with high computation speed and throughput. They are oriented for high computation demanding applications with multiple exponential function computations.