Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization

Nowadays some High Level Synthesis (HLS) tools are introduced which are able to generate Hardware Description Language (HDL) codes from high level floating point arithmetic expressions for implementation on FPGAs. Before this conversion, changing the form of high level expressions usually leads to significant improvements in the final implementation in terms of accuracy, resource usage and latency. In this paper, we introduce a method to find better forms of a floating point arithmetic expression in terms of accuracy, resource usage and delay. We first come up with a solution to estimate delay and resource usage in an FPGA for a specific expression. Then we extract equivalent expressions by iterative factorization and to reduce the complexity, we select only those expressions generated by associativity rule which are better in terms of accuracy. Finally, we propose an algorithm to choose expressions from the set of equivalent expressions in terms of accuracy, resource usage and delay while let designers apply their accuracy, area and delay constraints. The results show that our proposed method in comparison with existing methods such as SOAP [10], has up to 35.2% overall improvement in terms of runtime for generating expressions and choosing expressions from the set of final expressions.