• DocumentCode
    3679167
  • Title

    Sub-Threshold Design and Architectural Choices

  • Author

    Christian Piguet;Marc Pons; Séverac

  • Author_Institution
    Centre Suisse d´Electron. et Microtech. SA, Neuchatel, Switzerland
  • fYear
    2015
  • fDate
    7/1/2015 12:00:00 AM
  • Firstpage
    481
  • Lastpage
    484
  • Abstract
    Standard cell design and memory design need to be optimized for sub-threshold operation. It is interesting to revisit digital block architectures when implemented using these sub-threshold basic bricks. Out of many possible architectures for the same logic function (i.e. Multiplier), it turns out that there are optimal sub-threshold architectures.
  • Keywords
    "Computer architecture","Microprocessors","Adders","Power demand","Transistors","Standards","Delays"
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2015 IEEE Computer Society Annual Symposium on
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2015.58
  • Filename
    7309617
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3679167