Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops

Soft errors are becoming a major concern in integrated circuits fabricated in nanometer technology working in dependable applications. The goal of this paper is to determine the dependency of soft errors in integrated circuits with its operating frequency and variety of delays in the combinational logic paths. Each circuit flip-flop has a different Time Vulnerability Factor (TVF) that can be measured by electrical simulations based on the delay of the combinational logic path that is connected to that flip-flop. The TVF values of the master and slave latches can vary from 50% to 0% of the clock period according to the logic propagation delay and slack presented in the circuit, the operating frequency and technology process. In this work, the analysis was performed by electrical simulation using sequential designs described in 16nm, 22nm and 32nm nanometer technologies. Results show that the probability of SEU occurrence decreases with the increase of frequency and flips-flops connected to the critical paths present the lowest TVFs. This information can be easily integrated in design tools to help identifying the most vulnerable flip-flops in circuits before mitigate or replace the flip-flops by radiation hardened ones.