A Linear Comparator-Based Fully Digital Delay Element

A linear delay element is proposed in 0.18 μm CMOS technology with a power supply of 1.8V. The proposed delay element maintains linearity over a relatively large input voltage range of 1.2V and its delay range (sensitivity) can be tuned through a bias voltage. Its power dissipation is 50μW at a clock frequency of 1GHz and its robustness in different process corners has been shown through simulations. Additionally, a 6bit 107MS/s Fully Digital ADC with 1.2 V input range has been implemented using the proposed delay element. The simplicity of design and functioning of the proposed delay element contributes to its improved power and energy consumption.