Built-In Self Optimization for Variation Resilience of Analog Filters

At deep sub-micron integrated circuit technologies and beyond, characteristics of analog circuits are increasingly affected by process variations and device aging. Although design-time approaches are able to take these effects into account, it is very difficult for a single static design to efficiently handle all kinds of variation scenarios. In this work, a built-in self optimization technique is developed such that each analog IC chip can autonomously improve its performance in the presence of significant variations. As a demonstration, an on-chip analog self-test platform is implemented to test an active-RC band-pass filter, whose components can be reconfigured to obtain different frequency responses. The desired response is found by a digital circuit implementation of multi-start meta-heuristic optimization. The proposed technique does not rely on external test equipment or any general purpose digital signal processor. Its effectiveness is confirmed by simulations as well as measurement results from a test-chip fabricated in 180 nm CMOS technology.