Design recommendations to mitigate memory and cache non-determinisms in multi-core based IMA platform of airborne systems

The adoption of multi-core processors in airborne safety-critical systems has been troublesome to the aeronautic industry. This type of processor inserts new sources of non-determinism on application execution, increasing difficulty to perform safety analysis that relies on Worst-Case Execution Time (WCET). Design recommendations to mitigate non-determinism in airborne multi-core systems are presented in this work. A prototype of platform was constructed in order to demonstrate feasibility of non-determinism mitigation recommendations. We utilized the prototype to experiment with parallel memory access. The recommendations are a sound basis to allow multi-core processors to be used in airborne systems, however, some changes are required.