Title :
Design of 1Mbit RRAM memory to replace eFlash
Author :
Wouter Diels;Alexander Standaert
Author_Institution :
Department of Electrical Engineering, Katholieke Universiteit Leuven, 3001 Heverlee, Belgium
Abstract :
A 1Mbit RRAM memory robust against variations in 45nm technology is presented. The focus lies on read reliability. To overcome variability a tuned reference signal is generated by connecting multiple reference cells in parallel. A bitline load has been designed to obtain maximum bitline voltage difference. Sense amplifier performance has been improved by allowing overlap between passgate-enable and latch-enable signals, this overlap gives rise to a nonlinear phenomenon, the RC-latch-effect. Write operation has not been included in the design and the results are based on circuit simulations.
Keywords :
"Transistors","Memristors","Capacitance","Integrated circuit modeling","Reliability","Ash"
Conference_Titel :
EUROCON 2015 - International Conference on Computer as a Tool (EUROCON), IEEE
DOI :
10.1109/EUROCON.2015.7313804
