• DocumentCode
    3682277
  • Title

    28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors

  • Author

    Fady Abouzeid;Sylvain Clerc;Cyril Bottoni;Benjamin Coeffic;Jean-Marc Daveau;Damien Croain;Gilles Gasiot;Dimitri Soussan;Philippe Roche

  • Author_Institution
    STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles Cedex, France
  • fYear
    2015
  • Firstpage
    108
  • Lastpage
    111
  • Abstract
    This paper presents the technology and design optimization performed in 28nm FD-SOI to reach ultra-low energy and/or soft-error tolerance on ARM® Cortex®-M4 32bits processors. A 8.9pJ per cycle efficiency was measured while performing at 0.5V/45MHz, and a soft-error immunity was measured under alpha and neutron radiation while performing at 1.0V/730MHz. These results were achieved by the design of specific standard cells, macros and clock tree architectures, the technology intrinsic performances, and an adapted CAD flow.
  • Keywords
    "Program processors","Clocks","Standards","Transistors","Low voltage","Robustness"
  • Publisher
    ieee
  • Conference_Titel
    European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4673-7470-5
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2015.7313840
  • Filename
    7313840
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3682277