DocumentCode :
3682322
Title :
A 0.8–3 GHz mixer-first receiver with on-chip transformer balun in 65-nm CMOS
Author :
Tero Tikka;Kari Stadius;Jussi Ryynänen;Mikko Kaltiokallio
Author_Institution :
Department of Micro and Nanosciences, Aalto University, Espoo, Finland
fYear :
2015
Firstpage :
295
Lastpage :
298
Abstract :
This paper describes a wide-band receiver designed to be connected directly to a single-ended non-50 ohm antenna. The receiver is based on a four-phase mixer-first architecture and it includes an on-chip transformer balun. Reconfigurability in the balun extends the low-end operation band by 300 MHz. This design demonstrates that with an on-chip balun it is possible to achieve comparable performance to a similar receiver with an external high-performance balun. The receiver is implemented in 65-nm CMOS and it operates in 0.8-3 GHz band with 40 dB gain and 7 dB noise figure.
Keywords :
"Receivers","Mixers","Impedance matching","Gain","Noise measurement","Noise","Capacitance"
Publisher :
ieee
Conference_Titel :
European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st
ISSN :
1930-8833
Print_ISBN :
978-1-4673-7470-5
Type :
conf
DOI :
10.1109/ESSCIRC.2015.7313885
Filename :
7313885
Link To Document :
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