DocumentCode :
3682330
Title :
A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration
Author :
Koki Tanaka;Ryo Saito;Hiroki Ishikuro
Author_Institution :
Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan
fYear :
2015
Firstpage :
327
Lastpage :
330
Abstract :
A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. “Memory effect” caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.
Keywords :
"Attenuation","Pipelines","Calibration","Clocks","Capacitors","Synthetic aperture radar","Timing"
Publisher :
ieee
Conference_Titel :
European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st
ISSN :
1930-8833
Print_ISBN :
978-1-4673-7470-5
Type :
conf
DOI :
10.1109/ESSCIRC.2015.7313893
Filename :
7313893
Link To Document :
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