Low voltage error resilient SRAM using run-time error detection and correction

An adaptive SRAM architecture that can dynamically detect and correct read and write failures is discussed. The proposed method detects the failures, extends the failing cycles and subsequently corrects those. Data in the failing clock cycle are discarded and are made available in the subsequent cycle, if the failure is corrected. To detect write failures an adaptive write technique based on dummy write column is used. While for the read failures, the proposed read technique uses two non-identical sense amplifiers. We could achieve a Vmin lowering of 180mV for a 90nm ultra low power, high density 6T CMOS SRAM with less than 0.1 percent impact on throughput. This has been achieved without using assist-circuits or ECC. Area overhead is 3 percent for a 128Kb memory instance.