DocumentCode
3682352
Title
A BIST structure for the evaluation of the MOSFET gate dielectric interface state density in post-processed CMOS chips
Author
Norman Dodel;Stefan Keil;Andreas Wiemhöfer;Malte Kortstock;Philipp Scholz;Uwe Kerst;Roland Thewes
Author_Institution
Chair of Sensor and Actuator Systems, Faculty of EECS, TU Berlin, Berlin, Germany
fYear
2015
Firstpage
412
Lastpage
415
Abstract
A highly accurate built-in-self-test (BIST) structure is presented which reveals the gate dielectric interface state density of the MOS transistors of CMOS chips. A specific measurement setup or equipment is not required. The interface state density is directly A/D converted. The structure can be easily integrated into any chip with a standard digital interface.
Keywords
"Interface states","Logic gates","Built-in self-test","Charge pumps","Stress"
Publisher
ieee
Conference_Titel
European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st
ISSN
1930-8833
Print_ISBN
978-1-4673-7470-5
Type
conf
DOI
10.1109/ESSCIRC.2015.7313915
Filename
7313915
Link To Document