Title :
An Incremental Timing-Driven flow using quadratic formulation for detailed placement
Author :
Guilherme Flach;Jucemar Monteiro;Mateus Fogaça;Julia Puget;Paulo Butzen;Marcelo Johann;Ricardo Reis
Author_Institution :
Universidade Federal do Rio Grande do Sul (UFRGS) - Instituto de Informá
Abstract :
In this work, we present a flow for the Incremental Timing-Driven Placement problem. Given a legal placement, the aim is to reduce the circuit´s timing violations without changing significantly the cell density, subject to a maximum displacement constraint. Our flow consists of two core steps: useful clock skew optimization and critical path fine tuning. During useful clock skew optimization, sequential cells are replaced, seeking to minimize clock skew. After that, a quadratic formulation is used to further reduce critical path delays. An incremental legalization tool is also presented, which supports the methods developed in this work. Our Incremental Timing-Driven Placement flow can achieve, on average, 0.3%, 26.2%, 8.7% and 23.7% of the normalized quality score improvement compared to state-of-the-art algorithms.
Keywords :
"Clocks","Optimization","Logic gates","Delays","Mathematical model","Runtime"
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2015 IFIP/IEEE International Conference on
Electronic_ISBN :
2324-8440
DOI :
10.1109/VLSI-SoC.2015.7314382