DocumentCode
3682790
Title
Power-management high-level synthesis
Author
Dominik Macko;Katarína Jelemenská;Pavel Cicák
Author_Institution
Faculty of Informatics and Information Technologies, Slovak University of Technology, Bratislava, Slovakia
fYear
2015
Firstpage
63
Lastpage
68
Abstract
Power management is an integral part of almost every new system design. It enables to keep the power under constrains, implementing such power-reduction techniques as power gating, multi-voltage design, or voltage and frequency scaling. Due to the complexity of modern designs, the system level of abstraction is adopted as a design starting point. However, the power management is not yet fully adopted at such abstraction level. In the previous research, we have proposed the abstract power-management specification, simplifying its adoption by an order of magnitude. This paper targets the power-management high-level synthesis, closing thus the gap between the system-level power management and its standard form at lower abstraction levels. Such design automation enables to reduce a number of human errors, potentially introduced by manual design. The presented experimental results validate the proposed approach.
Keywords
"Standards","Switches","Clocks","Ports (Computers)","Registers","Frequency-domain analysis","Analytical models"
Publisher
ieee
Conference_Titel
Very Large Scale Integration (VLSI-SoC), 2015 IFIP/IEEE International Conference on
Electronic_ISBN
2324-8440
Type
conf
DOI
10.1109/VLSI-SoC.2015.7314393
Filename
7314393
Link To Document