Cost reduction of system-level tests with stressed structural tests and SVM

System tests with boards are applied to capture defects in functional modes. Yet, these tests are usually costly with limitation on the production throughputs. Stressed structural tests (patterns produced by traditional ATPG) have been proposed to correlate with system tests and to replace them in production. However, due to low confidence level (small experimental samples and volatile chip variability conditions), we need a process to tune and apply stressed tests gradually. In this paper, we use SVM to classify stressed tests with the goal to select high-quality chips without the need of further system tests. The remaining (smaller batch of) chips will be processed by system tests for further defect screening. The proposed SVM method can be flexible in tuning the relative size of chip partitions.