Design and analysis of search algorithms for lower power consumption and faster convergence of DAC input of SAR-ADC in 65nm CMOS

We propose a new approach in reducing the power consumption of the Successive approximation register Analog to Digital Converter (SAR-ADC) by changing the convergence algorithm of the Digital to Analog converter (DAC) input of the SAR-ADC. Different search algorithms such as binary search tree, moving binary search tree (BST), least significant bit shifter (LSB), adaptive algorithm and split-register moving BST algorithm are designed and analyzed for faster convergence of the DAC input. In this paper, we design a 0.8 GS/s, 8 bit (Effective number of bits (ENOB) - 7.42), 8.352 mW SAR ADC with a proposed moving BST algorithm in 65nm CMOS which ranks amongst the current state of the art ADCs with a FOM 65.25fJ/step.