• DocumentCode
    3683099
  • Title

    Design and optimization on ESD self-protection schemes for 700V LDMOS in high voltage power IC

  • Author

    Zhong Chen;Akram Salman;Guru Mathur;Gianluca Boselli

  • Author_Institution
    University of Arkansas, Electrical Engineering, Fayetteville, 72701, USA
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper presents an ESD self-protection scheme for a 700V high-voltage laterally diffused metal-oxide-semiconductor (LDMOS) field effect transistor. The safe operating area (SOA) and breakdown failure mechanism of 700V LDMOS are analyzed using simulations and experimental results. The scalability of thermal failure current with LDMOS width is also demonstrated.
  • Keywords
    "Logic gates","Electrostatic discharges","Transient analysis","Immune system","Electric potential","Robustness"
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2015 37th
  • Type

    conf

  • DOI
    10.1109/EOSESD.2015.7314735
  • Filename
    7314735
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3683099