• DocumentCode
    3683245
  • Title

    Chip-level anti-reverse engineering using transformable interconnects

  • Author

    Shuai Chen;Junlin Chen;Domenic Forte;Jia Di;Mark Tehranipoor;Lei Wang

  • Author_Institution
    Department of Electrical and Computer Engineering, University of Connecticut, Storrs, 06269, USA
  • fYear
    2015
  • Firstpage
    109
  • Lastpage
    114
  • Abstract
    Cloning of integrated circuit (IC) chips have emerged as a significant threat to the semiconductor industry. Unauthorized extraction of design information from IC chips can be carried out in numerous ways. Invasive methods physically disassemble chip package and gain access to the different layers of a die through the low-cost delaying processing. This paper presents a new countermeasure exploiting transformable IC technologies. Transformable ICs are fabricated using materials that not only are electronically active but also change their electrical properties and physical compositions when experiencing invasive attacks. Simulation results demonstrate the proposed approach in improving the complexity of chip reverse engineering without introducing large performance overhead.
  • Keywords
    "Integrated circuit interconnections","Logic gates","Reverse engineering","Correlation","Complexity theory","Timing"
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on
  • Type

    conf

  • DOI
    10.1109/DFT.2015.7315145
  • Filename
    7315145