Title :
Piecewise-functional broadside tests based on intersections of reachable states
Author_Institution :
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, U.S.A.
Abstract :
A characterization of broadside tests as p-way piecewise-functional broadside tests, for p ≥ 1, partitions the scan-in state of a broadside test into substates of p reachable states. This provides an indication of the proximity to functional operation conditions during the functional clock cycles of the tests. It is important for avoiding excessive power dissipation and overtesting of delay faults. This paper makes the new observations that the intersections of subsets of p reachable states can be used for guiding the generation of p-way piecewise-functional broadside tests. In addition, subsets of p reachable states with larger intersections allow more tests to be generated. The paper describes a logic simulation based procedure for computing subsets of reachable states with large intersections, and a test generation procedure based on these observations.
Keywords :
"Circuit faults","Switches","Computational modeling","Benchmark testing","Delays","Fault tolerance","Fault tolerant systems"
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on
DOI :
10.1109/DFT.2015.7315150