Optimal implementation of an integer divider using multifunctional registers with decoded control inputs

The authors propose a new optimal method for the implementation of an integer division sequential algorithm using multifunctional registers (MFR) with decoded control inputs, based on transfer matrix method. The implementation cost is calculated emphasizing the most economical solutions. Low cost means less power consumed - green architectures, the CPU FPU logic core is much faster and the responses timing are short. The modern design tools handle digital systems with many outputs and represent them by cubes, for efficiency reasons. Talking as optimal, the implementation of the digital automaton can be reduced to a combinatorial one: synthesis using logic gates primitives and using floor planning design. The digital logic network that generates the control signals of the Finite State Machine (FSM) can be synthesized using the transfer matrix.