Logic synthesis method for combinatorial blocks using a FPGA-like basic cell structure

The paper presents a method for completing the logic synthesis stage of the design flow applied to a FPGA-like technology. The method presented is focused on combinatorial blocks included into the design, as the propagation delay associated to these blocks influences the performance of the future chip directly. It has to be said that the method presented in this paper is a heuristic technique, starting from the structure of the basic cell in a FPGA-like technology. The dedicated optimization tools perform the synthesis are using a library of simple logic functions, then run an algorithm for packing as many gates from the output netlist as possible using the physical resources of the technology.